“Margin is basically a calculation of risk, and it is something impossible for a human to do.” explains Aart de Geus, managing director of chip design software maker Synopsys. “A machine will optimize everything. Everything.”

Artificial intelligence is increasingly used in semiconductor design, and one of its benefits is that AI technology will explore design tradeoffs that humans would refuse to even consider.

Take for example the concept of margin. Designers will leave room for error when placing circuits on a chip, to anticipate manufacturing errors that could skew the timing of a signal making its way around the chip. A human wants to leave as little room for error as possible. A machine will be more daring.

“Margin is basically a calculation of risk, and it is something impossible for a human to do.” explains Aart de Geus, managing director of chip design software maker Synopsys.

“A machine will optimize everything. Everything.”

De Geus spoke to ZDNet ahead of a keynote address he will deliver at the annual Hot Chips for Advanced Computing Conference on Monday. The conference is being held virtually this year.

Also: AI on the bench: Cadence offers machine learning to smooth chip design

De Geus explained to ZDNet an expansion of AI technology into the company’s software that has been in the works for several years.

The program, called DSO.ai, was first introduced a year ago in May. This program was originally able to optimize the layout of circuits in the chip floor plan, the way the two-dimensional area is used.

The topic of de Geus’ talk is how Synopsys extends beyond optimizing the physical layout of a chip to optimize other factors. One is what is called architecture.

A chip architecture refers to what types of circuits and what types of functional blocks are to be used on the chip, such as arithmetic logic units, caches, registers, and pipelines.

“Quite recently we have moved to the early stages of micro-architectural decisions, and so, for example, we can now also optimize the floor plan and the timing scheme,” said de Geus.

In addition to the layout of the physical circuits and the architectural decisions, Synopsys is now working on a third optimization vector, called the functional aspect, or behavior, of the chip.

Also: Future of chipmaking will rely heavily on AI to spot flaws, according to Applied Materials

This includes developing a kind of feedback loop where the software that will ultimately be executed by the chip is modeled as a variable against which to optimize the logical and physical design.

“One breakthrough that I honestly thought wasn’t going to be easily achievable is that we now also have the ability to look at the software that’s going to be running on the chip, to do an analysis of expected peaks in usage, hot times. power, and optimize the chip against that, ”explained de Geus.

The ultimate goal is to set requirements for the chip design program and let it figure it out on its own.

“Start with the chip specs, make architectural decisions, we automate everything else,” is how de Geus likes to describe the vision.


During the initial use of the three vectors, de Geus said that Synopsys saw a “hyper-scaler chip,” the sort of thing that would be used in a data center for massive types of computation – including AI – which could have its electricity consumption reduced by 27%.

“The power has been reduced, but now when you can access the software you are in a different league because the power reduction has always been difficult, but it is extremely difficult to estimate it,” said de Geus. Chips are like a faucet: when inactive they can have small drops, leakage power, which is a relatively stable thing to measure, he said. But dynamic power, similar to opening and closing a faucet, has much less predictability.

“Power is, in my opinion, the most difficult physical characteristic of anything we do,” said de Geus. “Because it literally goes from the very nature of the materials used in manufacturing, from the configuration of a single transistor, etc., to the scope of application.”

Samsung is the first Synopsys customer to report having manufactured a chip optimized with DSO.ai software.

Synopsys’ tool is based on a form of machine learning called reinforcement learning. This technology has been used successfully by Google’s DeepMind unit to carry out the Alpha Zero program.

Over the past couple of years, Google has extended machine learning to automate chip design, just the first vector, the physics. “Google is looking at the placement part, what we are optimizing is not the placement but the synthesis and timing and the physical and test optimization,” said de Geus. “The complexity is very great” in the design of the chips, he stressed.

Such automation through machine learning extends to all semiconductor participants. Synopsys’ big rival Cadence Design explained how their Cerebrus tool can deliver 20% or more improvements in chip performance, power consumption, and area utilization.

And Applied Materials, the world’s largest maker of semiconductor manufacturing tools by revenue, this year unveiled SEMVision, a defect inspection software that uses machine learning to classify types of defects on a silicon wafer so as to adapt to new information.

For de Geus, the spread of AI throughout the chip design toolchain is a natural consequence of the spread of AI to the world. The proliferation of data is accelerating the business of using chips to analyze everything, putting pressure on chip improvement.

“I always thought Moore’s Law was the ultimate push up – all of a sudden you can do things you couldn’t do before,” de Geus said. “Now people say, I’m doing a little machine learning which is great, but why are your chips so slow!”

The result, he says, is “Now this mountain [of Moore’s Law] is complemented by the opposite, which is that downward funnel – a technological push towards economic traction. “

Under the pressure of push and pull, AI could be the way to find new solutions to break the bottleneck, just as Alpha Zero found solutions humans have never seen in chess despite the obvious rules. for thousands of years.

“To me they’re not surprising, but to me they’re interesting,” de Geus said of the AI ​​approach to design.

“When you optimize everything, you reduce the margin in everything,” explained de Geus. “Except, there are a lot of places on the chip where you can actually increase the margin, and that statistically increases your return.”

Yield means how many good chips can be obtained from a single silicon wafer, the critical economic issue for all chipmakers and their suppliers such as Taiwan Semiconductor Manufacturing.

A greater margin of error is a tolerance for greater risk, but risk is, again, something that humans find difficult and often unacceptable.

This includes “risks when [humans] don’t know what the dependencies are with other parts of the design, ”said de Geus.

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